1. Field of the Invention
The present invention relates generally to the field of thin films. In particular, the invention concerns the production of doped nitride thin films. The present invention also comprises a method of modifying electrical and physical properties of nitride thin films produced by ALD (Atomic Layer Deposition). Films produced by the invention can be used in metal gate and metal electrode applications in metal oxide semiconductor field effect transistors (MOSFETs), in capacitor structures in memory applications and in barrier layers in interconnect structures.
2. Description of the Related Art
Atomic layer deposition (ALD) is a self-limiting process, whereby alternated pulses of reaction precursors saturate a substrate surface and leave no more than one monolayer of material per pulse. The deposition conditions and precursors are selected to ensure self-saturating reactions, such that an adsorbed layer in one pulse leaves a surface termination that is non-reactive with the gas phase reactants of the same pulse. A subsequent pulse of different reactants reacts with the previous termination to enable continued deposition. Thus, each cycle of alternated pulses leaves no more than about one molecular layer of the desired material. The principles of ALD type processes have been presented by T. Suntola, e.g. in the Handbook of Crystal Growth 3, Thin Films and Epitaxy, Part B: Growth Mechanisms and Dynamics, Chapter 14, Atomic Layer Epitaxy, pp. 601-663, Elsevier Science B.V. 1994, the disclosure of which is incorporated herein by reference.
In a typical ALD process for depositing thin films, one deposition cycle comprises exposing the substrate to a first precursor, removing unreacted first reactant and reaction byproducts from the reaction chamber, exposing the substrate to a second precursor, followed by a second removal step. Typically, halide precursors, such as TiCl4 and HfCl4, are used as precursors in ALD deposition because those precursors are inexpensive and relatively stable, but at the same time reactive towards different types of surface groups. H2O and NH3 are widely used for oxide and nitride deposition, respectively, as second precursors.
Atomic Layer Deposition of Ta(+III)N has been very challenging because of the multiple, stable oxidation states of Ta. Conventional ALD TaN processes using halides or metal organic Ta precursors and ammonia produces a dielectric film with Ta oxidation state of +V (Ta3N5). It is also possible to get stoichiometric TaN with metal halides by using Zn as reducing agent (Ritala, M., Kalsi, P., Riihelä, D., Kukli, K., Leskelä, M. and Jokinen, J., Chem. Mater. 11 (1999) 1712-1718.). However, this process is not favorable in IC industry because of zinc contamination. While metal halides are very stable, metal organic Ta-precursors tend to have poor thermal stability and therefore the film besides having a high resistivity can also have a lot of carbon as contaminant.
Attempts for silicon doping of ALD nitride thin films have been made (Min, J.-S. et al, J. Electrochem. Soc. 147 (2000) 3868-3872. However, the metal precursor (TDMAT, tetrakis(dimethylamido)titanium) that Min. et al. are not ideal for ALD deposition as Elam et al. (Elam, J. W., et al., Thin Solid Films 436 (2003) 145-156) have discovered. The titanium precursor that Min et al. used decomposes already at very low temperatures <180° C. and thus the deposited film will have too much impurities, for example, carbon and hydrogen. At those temperatures the other precursors, especially ammonia (NH3), is not reactive enough. Also monosilane (SiH4) that Min et al. used is not ideal as an ALD precursor, because it is very stable and not reactive enough. It is not ideal to use that precursor in ALD deposition. The addition of monosilane to the process also decreased the growth rate of the film.
Ta(Si)N films (Alén et al., J. Electrochem. Soc. 151 (2004), G523-G527) have been deposited by ALD. The silicon precursor, tris(dimethylamino)silane (TDMAS), that Alén et al. used is known to decompose quite easily at temperatures needed for ALD nitride film deposition. Also films deposited at 300° C. contained as much as 10 at-% chlorine and had resistivities in excess of 0.5 Ωcm. Therefore is TDMAS is not an applicable precursor for silicon doping of ALD nitride thin films.
Several attempts (for example, Klaus et al., Surf Sci. 418, (1998) L14-L19) have also been made for ALD of silicon nitride from chloride based silicon precursors, but either the reaction temperature (>500° C.) is too high for metal gate application, which can cause degradation of the gate dielectric layer, and also for barrier layer application in interconnect structures, in which the low-k materials degrades at those temperatures, or the deposition rate per time unit is so slow that there is no use of this process in production or the doses of precursor are extremely large, which will cause severe problems in purging, which again will led to problems like gas-phase growth of the film and generation of particles, the reactor between the pulses
Semiconductor devices are continuously improved to enhance device performance. For example, both smaller device size and higher speed of operation are highly desirable performance targets. Transistors have also been continuously reduced in size to lower the power consumption and to increase the clocking frequency. By constructing smaller gate structures for complementary metal oxide silicon (CMOS) transistors, it becomes possible to pack more transistors on the same surface area. The reduction in the size of the gate structures has led to a substantial decrease of the electrical thickness of the gate dielectric to 3 nm and less in today's technologies.
The main elements of a typical MOS semiconductor device are shown in FIG. 1. The device generally includes a semiconductor substrate 101, on which a gate stack is disposed. The gate stack comprises a gate dielectric layer 110 and a gate electrode 114 disposed on the gate dielectric layer 110. The gate electrode 114 acts as a conductor. An input signal is typically applied to the gate electrode 114 via a gate terminal (not shown). Lightly doped drain (LDD) regions 103 reduce the electric field near the drain edge and thus reduce the incident of hot carrier generation. Spacers 111, usually consisting of an insulating oxide, are formed in the sidewalls. Then, heavily doped source/drain regions 102 are formed in the semiconductor substrate 101 and are later connected to source/drain terminals (not shown).
A channel region 116 is formed in the semiconductor substrate beneath the gate dielectric 110 and it separates source/drain regions 102. The channel region is typically lightly doped with a dopant of a type opposite to that of the source/drain regions 102. The gate electrode 114 is separated from the semiconductor substrate 101 by the gate dielectric layer 110. The insulating gate dielectric layer 110 is provided to prevent current from flowing between the gate electrode 114 and the source/drain regions 102 or the channel region 116. The properties of the transistor critically depend on the thickness and quality of the gate dielectric layer 110.
In a CMOS device, opposite type NMOS 300 and PMOS 350 transistors are present as shown in FIG. 3. By applying a voltage to the gate electrodes 314, 364 of the transistors, channel regions 316, 366 become electrically conductive in the lightly doped substrate regions beneath the gate dielectrics 310, 360. The transistor switches from a non-conductive state into a conductive state at the threshold voltage that is applied to the gate electrode. In order to keep the threshold voltages of the transistors small and, hence, to keep the power consumption of the transistors low, the work function of the gate electrode material should be nearly equal to the work function of the substrate material underneath the gate electrode.
P-type and N-type substrate materials have significantly different work functions.
Traditionally, the work function matching was achieved by using polysilicon as gate electrode material and by doping the polysilicon with a dopant. However, in current technology, polysilicon is not adequate anymore because of its too low conductivity and because of depletion effects. Depletion takes place in the semiconducting polysilicon at the gate electrode/gate dielectric interface, increasing the equivalent oxide thickness (EOT) of the gate dielectric. On the other hand, the solubility of the dopants of the polysilicon is limited to about 5×1020 atoms/cm3. The solubility restricts the amount of charge carriers formed in polysilicon. Therefore, especially in the future more conductive materials, such as refractory metals, e.g. tungsten, are preferred. In practice, metallic materials have an infinite amount of carriers (5×1022 atoms/cm3) and therefore the thickness of the depletion region is virtually zero. This leads to a decrease of 4-5 Å of the EOT of the gate dielectric.
The most important property of the metal gate is its work function, which together with the doping level of the substrate determines the threshold voltage of the metal oxide semiconductor device. The work function of the metal electrode material should be about 4.0 to 4.2 eV in NMOS field effect transistors and about 5.0 to 5.2 eV in PMOS field effect transistors.
Features known to influence the work function of the metal electrode material are, in particular:                the method of depositing the metal electrode,        heat treatments carried out after the deposition (i.e. RTA, Rapid Thermal Annealing),        the thickness of the metal electrode layer, the gate oxide material used,        the crystal orientations and crystallinity of the electrode material, and        the electronic properties of channel region material        
The impact of the heat treatments on the work function of the electrode material is possibly due to crystallization of the materials or, for example, to emission of stoichiometrically superfluous nitrogen or some other element from the material during heat treatment. It is known that when a metal is oxidized or nitridized its average electronegativity is increased. Since work functions scale with electronegativity, an increase of the electronegativity also increases the work function.
Attempts have been made to modify the work functions of metal gate materials by doping them after deposition of the metal gate film. However, the work functions of metal gate materials after doping are not easily predictable and controllable. Doping of the gate material after deposition can change not only the stoichiometry of the film but also the crystal orientation of the films (Q. Lu et al., Symp. VLSI Tech. (2001) 45-46 and US Pat. Appl. No. 2002/0008257 A1).
U.S. Pat. No. 6,458,695 B1 discloses a method of adjusting the work function of an electrode by regulating the composition of the material. The publication describes the deposition of metal gates followed by oxidizing or implantation of oxygen into the metal gate electrode for one or both types of transistors so that an alloy is formed of the metal and its conductive oxide, the alloy having a desired work function.
U.S. Pat. No. 6,506,676 discloses a method of changing the work function of an electrode comprising titanium, aluminum and nitrogen by changing the composition of (TixAly)1-zNz. According to the method, atomic layer deposition can be used for changing the composition of the film. During the time between cycles when the (TixAly)1-zNz film is deposited using the precursors, one of NH3, N2 and ND3 may be used for purging materials in order to adjust the nitrogen (N) content. At this time, the composition of nitrogen (N) is controlled by the number of each of the cycles.
U.S. Pat. No. 6,518,106, Ngai et al., discloses a method of changing the composition and, thus, the work function of a gate electrode in a transistor with ALD by changing the concentration of one element in the gate electrode material. According to the method of U.S. Pat. No. 6,518,106 B2 the work function of a metal gate layer is changed when the concentration of silicon or nitrogen is changed in layers that contain metal, silicon and nitrogen (e.g. TaSiN). Atomic layer deposition (ALD), chemical vapor deposition (CVD) and physical vapor deposition (PVD) have been disclosed as examples of methods for depositing the metal gate layer. However, a method of avoiding local concentration variations over the substrate is not disclosed.
Ru—Ta-alloys have also been studied for use as gate electrodes. In the studies performed, the work function of the ruthenium-tantalum metal electrodes could be adjusted to a value between 4.2 and 5.1 eV by using different Ru—Ta compositions. The work function of metal electrodes containing more ruthenium was close to 5 eV and an electrode with the composition Ru0.60Ta0.40 had a work function of about 4.3 eV (H. Zhong et al. Appl. Phys. Lett. 78 (2001) 1134-1136). However, the electrodes were formed by PVD method, resulting in sputtering damage on the gate stack dielectric layer and, furthermore, causing non-uniformities in electrical and physical properties of ultra-thin films over the substrate.
Tuning of the work function of an electrode can also be achieved by a two-layer electrode structure, each layer having a different work function as described in a U.S. Pat. No. 6,373,111. When the bottom electrode layer is thin, particularly below 3 nm, the work function of the electrode structure will primarily be determined by, and be equal to, the work function of the top layer. When the bottom layer is thick, e.g. above 10 nm, the work function of the electrode structure will primarily be determined by, and equal to, the work function of the bottom layer. In a transition region, between 3 and 10 nm, the work function of the electrode structure can be adjusted between the work function of the top layer and the work function of the bottom layer by adjusting the thickness of the bottom film.
Crystal orientation has a significant effect on the work function of the gate electrode. For example, tungsten with a crystallite orientation of 110 (W<110>) has a maximum work function value of 5.25 eV and W<113> a minimum work function value of 4.18 eV (H. B. Michaelson, J. Appl. Phys. 48 (1977) pp. 4729-4733). This indicates that it is theoretically possible to make both gate electrodes of CMOS devices from the same material, because the acceptable limit is 4.0-4.2 eV for NMOS and 5.0-5.2 eV for PMOS.
It has been observed that by implanting the gate electrode material with 1-2 at.-% of nitrogen and after some annealing the work function value of the gate electrode changed so much that the change could not be explained by only the increased nitrogen concentration (R. Lin et al., IEEE Electron Dev. Lett. 23 (2002) pp. 49-51).
A problem associated with the known methods of tuning the work function of a gate stack is that several variables are involved simultaneously, which makes it very difficult to control the tuning. The composition of the gate electrode is one of the major factors affecting the work function. However, gate electrode layers having the same thickness and same chemical compositions, but deposited by different depositing techniques, such as PVD and ALD, still have different work functions. Another problem of the above-described methods is that adequate control of film composition, uniformities and profiles, or thickness cannot be achieved. Further, when the gate electrode material is contacted with an oxidizing ambient, the gate dielectric material is also subjected to the oxidizing ambient, which might detrimentally affect the dielectric material and oxidize the underlying substrate material.
The PVD method for metal gate deposition has several disadvantages; it can destroy the underlying gate dielectric and ruin the electrical properties of the transistor. Deposition of ultra thin and uniform films over the large surface area substrate is not possible; and due to poor step coverage the deposition of metal gates for three-dimensional transistor structures, like FinFET and tri-gate structures, is not possible at all. Therefore, a better deposition method, like ALD, which does not suffer from any of these disadvantages, is needed.
There is a need for a method of adjusting the work function of a gate electrode material in a gate stack and a method that avoids the above-described disadvantages.